The present invention relates to semiconductor fabrication processes and semiconductor devices. More particularly, the invention relates to a method of forming field effect transistors with silicide-containing gates.
Field effect transistors (“FETs”) can be fabricated with gates that include a silicide. The silicide increases conductivity, can decrease capacitance along the length of the gate conductor and can help decrease the amount of time required to turn on the transistor.
Conventionally, the gate of a FET can include a semiconductor, e.g., polycrystalline silicon (“polysilicon”) or other polycrystalline semiconductor material contacting a gate dielectric layer of the FET. A silicide layer may then occupy an overlying portion of the gate in contact with the semiconductor layer. The semiconductor material, e.g., single-crystal silicon, although heavily doped, is relatively resistive, typically having much higher sheet resistance, contact resistance and parasitic resistance than silicide. Typically, these resistance values of silicon are more than 10 times the comparable resistance values of commonly employed silicides.
In complementary metal oxide semiconductor (“CMOS”) technology circuits, n-type channel FETs (NFETs) and p-type channel FETs (PFETs) are situated in close proximity to each other and cooperate closely together to perform a circuit function. The performance of a PFET can be improved through use of a compressive stressor layer in close proximity to the channel of the PFET. The performance of an NFET can be improved through use of a tensile stressor layer in close proximity to the channel of the NFET.
U.S. Pat. No. 6,562,718 to Xiang et al. (“the '718 patent”) describes a method of forming a full silicide gate. A characteristic of the process described in the '718 patent is the use of chemical mechanical polishing (“CMP”) to expose the gate conductor after forming a shield layer for protecting the source and drain regions from further silicidation. One concern about using CMP is that the depth of recess cannot be controlled very well. The depth of recess can vary between different devices. In addition, the gates of some PMOS and NMOS devices may be recessed insufficiently or even excessively. In either case, the yield of microelectronic chips produced by such method can be negatively affected.
The article by A. Veloso et al., entitled “Dual Work Function Phase Controlled Ni-FUSI CMOS (NiSi NMOS, Ni2Si or Ni31Si12 PMOS): Manufacturability, Reliability & Process Window Improvement by Sacrificial SiGe Cap,” describes a method of forming full silicide gates of PMOS and NMOS transistors, each with a respective workfunction. However, like the method taught by the '718 patent, CMP is used to expose the polycrystalline semiconductor material (SiGe) of the cap layer. The Veloso et al. Article method also does not describe a method for forming dual stress liners for CMOS transistors having full silicide gates.